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1 for more information www.analog.com document feedback typical application features description dual ultrathin 2a or single 4a step-down dc/dc module regulator the lt m ? 4622a is a complete dual 2a step-down switching mode module ? (micromodule) regulator in a tiny ultrathin 6.25mm 6.25mm 1.82mm lga and 2.42mm bga pack - ages. included in the package are the switching controller, power fet s, inductor and support components. operating over an input voltage range of 3.6v to 20v, the LTM4622A supports an output voltage range of 1.5v to 12v, set by a single external resistor. its high efficiency design delivers dual 2a continuous, 3a peak, output current. only a few ceramic input and output capacitors are needed. the ltm4622 a supports selectable burst mode operation and output voltage tracking for supply rail sequencing. its high switching frequency and current mode control enable a very fast transient response to line and load changes without sacrificing stability. fault protection features include input overvoltage, output overcurrent and overtemperature protection. the ltm4622 a is available with snpb (bga) or rohs compliant terminal finish. product selection guide part number v in range v out range i out ltm4622 3.6v to 20v 0.6v to 5.5v dual 2.5a or single 5a LTM4622A 1.5v to 12v dual 2a or single 4a 3.3v and 5v dual output dc/dc step-down module regulator 12v input, 3.3v and 5v output, efficiency vs load current applications n complete solution in <1cm 2 n wide input voltage range: 3.6v to 20v n 1.5v to 12v output voltage n dual 2a (3a peak) or single 4a output current n 1.5% maximum total output voltage regulation error over load, line and temperature n current mode control, fast transient response n external frequency synchronization n multiphase parallelable with current sharing n output voltage tracking and soft-start capability n selectable burst mode ? operation n overvoltage input and overtemperature protection n power good indicators n 6.25mm 6.25mm 1.82mm lga and 6.25mm 6.25mm 2.42mm bga packages n general purpose point-of-load conversion n telecom, networking and industrial equipment n medical diagnostic equipment n test and debug systems all registered trademarks and trademarks are the property of their respective owners. b r r r r r b lt m4622a rev b 1.4 1.6 1.8 2.0 70 75 80 85 90 95 load current (a) 100 efficiency (%) 4622a ta01b v out = 5v v out = 3.3v 0 0.2 0.4 0.6 0.8 1 1.2
2 for more information www.analog.com pin configuration absolute maximum ratings v i n1 , v i n2 ................................................... C 0. 3v to 22v v out ........................................................... C 0. 3v to 16v pgoo d1 , pgoo d2 ..................................... C 0.3v to 18v ru n1 , ru n2 .................................... C 0.3v to v in + 0.3v intv cc , track/s s1 , track/s s2 ............ C 0.3v to 3.6v sync/mode, com p1 , com p2 , fb1 , fb2 ........................................... C 0.3v to intv cc operating internal temperature range (note 2) ............................................. C 40 c to 125 c storage temperature range .................. C 55 c to 125 c peak solder reflow body temperature ................. 26 0 c (note 1) (see pin functions, pin configuration table) order information part number pad or ball finish part marking* package type msl rating tempera ture range (note 2) device finish code lt m4622aev#pbf au (rohs) lt m4622av e4 lga 4 C40c to 125c lt m4622aiv#pbf au (rohs) lt m4622av e4 lga 4 C40c to 125c lt m4622aey#pbf sac305 (rohs) lt m4622ay e1 bga 4 C40c to 125c lt m4622aiy#pbf sac305 (rohs) lt m4622ay e1 bga 4 C40c to 125c lt m4622aiy snpb (63/37) lt m4622ay e0 bga 4 C40c to 125c consult marketing for parts specified with wider operating temperature ranges. *device temperature grade is indicated by a label on the shipping container. pad or ball finish code is per ipc/jedec j-std-609. ? pb-free and non-pb-free part markings: www.linear.com/leadfree ? recommended lga and bga pcb assembly and manufacturing procedures: www.linear.com/umodule/pcbassembly ? lga and bga package and tray drawings: www.linear.com/packaging r b r b r r b r t jmax = 125c, jctop = 17c/w, jcbottom = 11c / w, jb + ba = 22c/w, ja = 22c/w, weight = 0.21g bga package 25-lead (6.25mm 6.25mm 2.42mm) top view comp2 sync/ mode freq v out1 fb1 pgood1 track/ss1 a 5 1 2 3 4 pgood2 fb2 track/ss2 intv cc run2 b c d e comp1 gnd gnd run1 gnd v in1 v in1 v in2 v in2 v out2 t jmax = 125c, jctop = 17c/w, jcbottom = 11c / w, jb + ba = 22c/w, ja = 22c/w, weight = 0.25g http://www.linear.com/product/LTM4622A#orderinfo lt m4622a rev b
3 for more information www.analog.com electrical characteristics the l denotes the specifications which apply over the specified internal operating temperature range (note 2). specified as each individual output channel at t a = 25c, v in1 = v in2 = 12v, unless otherwise noted per the typical application shown in figure?27. symbol parameter conditions min typ max units switching regulator section: per channel v in1 input dc voltage range l 3.6 20 v v in2 input dc voltage range 3.6v < v in1 < 20v l 1.5 20 v v out(range) output voltage range v in1 = v in2 = 3.6v to 20v l 1.5 12 v v out(dc) output voltage, total variation with line and load c in = 22f, c out = 100f ceramic, r fb = 40.2k, mode = int v cc ,v i n1 = v i n2 = 3.6v to 20v, i out = 0a to 2a l 1.477 1.50 1.523 v v run run pin on threshold run threshold rising run threshold falling 1.20 0.97 1.27 1.00 1.35 1.03 v v i q(vin) input supply bias current v in1 = v in2 = 12v, v out = 1.5v, mode = gnd v in1 = v in2 = 12v, v out = 1.5v, mode = intv cc shutdown, run1 = run2 = 0 7 500 45 ma a a i s(vin) input supply current v in1 = v in2 = 12v, v out = 1.5v, i out = 2a 0.32 a i out(dc) output continuous current range v in1 = v in2 = 12v, v out = 1.5v (note 3) l 0 2 a v out(line) /v out line regulation accuracy v out = 1.5v, v in1 = v in2 = 3.6v to 20v, i out = 0a l 0.01 0.1 %/v v out(load) /v out load regulation accuracy v out = 1.5v, i out = 0a to 2a l 0.2 1.0 % v out(ac) output ripple voltage i out = 0a, c out = 100f ceramic, v in1 = v in2 = 12v, v out = 1.5v 5 mv v out(start) turn-on overshoot i out = 0a, c out = 100f ceramic, v in1 = v in2 = 12v, v out = 1.5v 30 mv t start turn-on time c out = 100f ceramic, no load, track/ss = 0.01f , v in1 = v in2 = 12v, v out = 1.5v 1.25 ms v outls peak deviation for dynamic load load: 0% to 50% to 0% of full load, c out = 100f ceramic, v in1 = v in2 = 12v, v out = 1.5v 100 mv t settle settling time for dynamic load step load: 0% to 50% to 0% of full load, c out = 100f ceramic, v in1 = v in2 = 12v, v out = 1.5v 20 s i outpk output current limit v in1 = v in2 = 12v, v out = 1.5v 3 4 a v fb voltage at fb pin i out = 0a, v out = 1.5v l 0.592 0.60 0.608 v i fb current at fb pin (note 4) 30 na r fbhi resistor between v out and fb pins 60.00 60.40 60.80 k i track/ss track pin soft-start pull-up current track/ss = 0v 1.25 a t ss internal soft-start time 10% to 90% rise time (note 4) 400 700 s t on(min) minimum on-time (note 4) 20 ns t off(min) minimum off-time (note 4) 45 ns v pgood pgood trip level v fb with respect to set output v fb ramping negative v fb ramping positive C8 8 C14 14 % % r pgood pgood pull-down resistance 1ma load 20 v intvcc internal v cc voltage v in1 = v in2 = 3.6v to 20v 3.1 3.3 3.5 v lt m4622a rev b
4 for more information www.analog.com electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTM4622A is tested under pulsed load conditions such that t j t a . the LTM4622Ae is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the full C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the LTM4622Ai is guaranteed to meet specifications over the full C40c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental?factors. symbol parameter conditions min typ max units v intvcc load reg intv cc load regulation i cc = 0ma to 50ma 1.3 % f osc oscillator frequency 1 mhz f sync frequency sync range with respect to set frequency 30 % i mode mode input current mode = intv cc C1.5 a note 3: see output current derating curves for different v in , v out and t a . note 4: 100% tested at wafer level. note 5: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. the l denotes the specifications which apply over the specified internal operating temperature range (note 2). specified as each individual output channel at t a = 25c, v in1 = v in2 = 12v, unless otherwise noted per the typical application shown in figure?27. lt m4622a rev b
5 for more information www.analog.com typical performance characteristics 1.5v output transient response 8v output transient response efficiency vs load current at 5v in efficiency vs load current at 12v in burst mode efficiency, 12v in , 1.5v out 5v output transient response 3.3v output transient response efficiency vs load current at 16v in 12v output transient response 50s/div load step 1a/div v out ac-coupled 50mv/div 4622a g05 v in = 12v, v out = 1.5v, f sw = 1mhz output capacitor = 47f 1 ceramic 10pf feed-forward capacitor load-step = 1a to 2a (10a/s) 50s/div load step 1a/div v out ac-coupled 50mv/div 4622a g06 v in = 12v, v out = 3.3v, f sw = 1mhz output capacitor = 47f 1 ceramic 10pf feed-forward capacitor load-step = 1a to 2a (10a/s) 50s/div load step 1a/div v out ac-coupled 100mv/div 4622a g07 v in = 12v, v out = 5v, f sw = 1mhz output capacitor = 47f 2 ceramic 10pf feed-forward capacitor load-step = 1a to 2a (10a/s) 50s/div load step 1a/div v out ac-coupled 100mv/div 4622a g08 v in = 12v, v out = 8v, f sw = 1.5mhz output capacitor = 47f 2 ceramic 10pf feed-forward capacitor load-step = 1a to 2a (10a/s) 50s/div load step 1a/div v out ac-coupled 100mv/div 4622a g09 v in = 16v, v out = 12v, f sw = 1.5mhz output capacitor = 47f 2 ceramic 10pf feed-forward capacitor load-step = 1a to 2a (10a/s) lt m4622a rev b 1.4 4622a g04 burst mode operation cmm 1.6 1.8 2.0 60 65 70 75 80 85 load current (a) 90 95 100 efficiency (%) 4622a g01 3.3v output, 1mhz 1.5v output, 1mhz load current (a) 0 0.2 0 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2.0 60 0.2 65 70 75 80 85 90 95 100 efficiency (%) 4622a g02 0.4 8v output, 1.5mhz 5v output, 1.5mhz 3.3v output, 1mhz 1.5v output, 1mhz load current (a) 0 0.2 0.4 0.6 0.8 0.6 1 1.2 1.4 1.6 1.8 2.0 60 65 70 75 0.8 80 85 90 95 100 efficiency (%) 4622a g03 3.3v output, 1mhz 1.5v output, 1mhz 12v output, 1.5mhz 1 8v output, 1.5mhz 5v output, 1.5mhz load current (ma) 0.001 0.01 0.1 1 10 0 10 1.2 20 30 40 50 60 70 80 90 100 efficiency (%)
6 for more information www.analog.com start-up with no load current?applied start-up with 2a load current?applied recover from short-circuit with no load current applied short-circuit with no load current applied short-circuit with 2a load current applied steady-state output voltage ripple typical performance characteristics 10ms/div v out 2v/div run 10v/div i in 0.5a/div 4622a g11 v in = 12v, v out = 3.3v, f sw = 1mhz output capacitor = 10f ceramic + 47f poscap soft-start cap = 0.1f 20s/div 4622a g14 i in 1a/div v out 2v/div v in = 12v, v out = 3.3v, f sw = 1mhz output capacitor = 10f + 47f poscap 10ms/div v out 2v/div run 10v/div i in 1a/div 4622a g10 v in = 12v, v out = 3.3v, f sw = 1mhz output capacitor = 10f ceramic + 47f poscap soft-start cap = 0.1f 20s/div 4622a g12 v out 2v/div i in 1a/div v in = 12v, v out = 3.3v, f sw = 1mhz output capacitor = 10f ceramic + 47f poscap 20s/div 4622a g13 v out 2v/div i in 1a/div v in = 12v, v out = 3.3v, f sw = 1mhz output capacitor = 10f + 47f poscap 20s/div v out ac-coupled 10mv/div 4622a g15 v in = 12v, v out = 3.3v, f sw = 1mhz output capacitor = 10f + 47f poscap lt m4622a rev b
7 for more information www.analog.com pin functions v in1 ( d3, e2), v in2 ( a2, b3): power input pins. apply input voltage between these pins and gnd pins. rec - ommend placing input decoupling capacitance directly between both v in1 and v in2 pins and gnd pins. please note the module internal control circuity is running off v in1 . channel 2 will not work without a voltage higher that 3.6v presents at v in1 . gnd (c1 to c2, b5, d5): power ground pins for both input and output returns. intv cc (c3): internal 3.3v regulator output. the internal power drivers and control circuits are powered from this voltage. this pin is internally decoupled to gnd with a 2.2f low esr ceramic capacitor. no additional external decoupling capacitor needed. sync/mode (c5): mode select and external synchroni - zation input. tie this pin to ground to force continuous s ynchronous operation at all output loads. floating this pin or tying it to intv cc enables high efficiency burst?mode operation at light loads. drive this pin with a clock to syn - chronize the ltm4622 a switching frequency. an internal phase-locked loop will for ce the bottom power nmoss turn on signal to be synchronized with the rising edge of the clock signal. when this pin is driven with a clock, forced continuous mode is automatically selected. v out1 ( d1, e1), v out2 ( a1, b1): power output pins of each switching mode regulator. apply output load between these pins and gnd pins. recommend placing output decoupling capacitance directly between these pins and gnd pins. freq ( c4 ): frequency is set internally to 1mhz . an external resistor can be placed from this pin to gnd to increase frequency, or from this pin to intv cc to reduce frequency. see the applications information section for frequency adjustment. package row and column labeling may vary among module products. review each package layout carefully. run1 (d2), run2 (b2): run control input of each switch - ing mode regulator channel. enables chip operation by tying run above 1.27v . tying this pin below 1v shuts down the specific regulator channel. do not float this pin. pgood1 (d4), pgood2 (b4): output power good with open-drain logic of each switching mode regulator channel. pgood is pulled to ground when the voltage on the fb pin is not within 8% (typical) of the internal 0.6v reference. track/ss1 ( e3), track/ss2 ( a3 ): output tracking and soft-start pin of each switching mode regulator channel. it allows the user to control the rise time of the output voltage. putting a voltage below 0.6v on this pin bypasses the internal reference input to the error ampli - fier, instead it servos the fb pin to the track voltage. above 0.6v , the tracking function stops and the internal reference resumes control of the error amplifier. there s an internal 1.4a pull-up current from intv cc on this pin, so putting a capacitor here provides soft-start function. a default internal soft-start ramp forces a minimum soft- start time of 400s. fb1 ( e4), fb2 (a4): the negative input of the error amplifier for each switching mode regulator channel. internally, this pin is connected to v out with a 60.4k preci - sion resistor. different output voltages can be programmed with an additional resistor between fb and gnd pins. in polyphase ? operation, tying the fb pins together allows for parallel operation. see the applications information section for details. comp1 (e5), comp2 (a5): current control threshold and error amplifier compensation point of each switch - ing mode regulator channel. the current comparators trip threshold is linearly proportional to this voltage, whose normal range is from 0.3v to 1.8v . tie the comp pins together for parallel operation. the device is internal compensated. do not drive this pin. lt m4622a rev b
8 for more information www.analog.com block diagram decoupling requirements symbol parameter conditions min typ max units c in external input capacitor requirement (v in = 3.6v to 20v, v out = 1.5v) i out = 2a 4.7 10 f c out external output capacitor requirement (v in = 3.6v to 20v, v out = 1.5v) i out = 2a 22 47 f figure?1. simplified LTM4622A block diagram power control fb2 60.4k 2.2f 0.1f 8.25k 0.22f 10f intv cc v out2 track/ss2 0.1f track/ss1 run1 run2 sync/mode comp1 0.1f v out1 v in1 v in2 10k pgood1 v out1 3.3v 2a v in 8v to 20v intv cc gnd 2.2h 4622a bd freq 324k internal comp comp2 fb1 60.4k 13.3k v out1 10k pgood2 intv cc 10f 47f 0.22f 0.1f v out2 v out2 5v 2a gnd 2.2h 47f internal comp lt m4622a rev b
9 for more information www.analog.com operation applications information the ltm4622 a is a dual output standalone non-isolated switch mode dc/dc power supply. it can deliver two 2a dc, 3a peak output current with few external input and output ceramic capacitors. this module provides dual precisely regulated output voltage programmable via two external resistor from 1.5v to 12v over 3.6v to 20v input voltage range. the typical application schematic is shown in figure?27. the ltm4622 a contains an integrated controlled on-time valley current mode regulator, power mosfets, inductors, and other supporting discrete components. the default switching frequency is 1mhz. for output voltages above 3.3v, an external resistor is required between freq and gnd pins to set the operating frequency to 1.5mhz to 2mhz to optimize inductor current ripple. for switching noise-sensitive applications, the switching frequency can be adjusted by external resistors and the module regulator can be externally synchronized to a clock within 30% of the set frequency. see the applications information section. with current mode control and internal feedback loop compensation, the ltm4622 a module has sufficient stability margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. current mode control provides cycle-by-cycle fast cur - rent limiting. an internal overvoltage and undervoltage comparators pull the open-drain pgood output low if the output feedback voltage exits a 8% window around the regulation point. furthermore, an input overvoltage protec - tion been utilized by shutting down both power mosfets when v in rises above 22.5v to protect internal devices. multiphase operation can be easily employed by connecting sync pin to an external oscillator. up to 6 phases can be paralleled to run simultaneously a good current sharing guaranteed by current mode control loop. pulling the run pin below 1v forces the controller into its shutdown state, turning off both power mosfets and most of the internal control circuitry. at light load currents, burst mode operation can be enabled to achieve higher efficiency compared to continuous mode (ccm) by set - ting mode pin to intv cc . the track/ss pin is used for power supply tracking and soft-start programming. see the applications information section. the typical ltm4622 a application circuit is shown in figure? 27. external component selection is primarily determined by the input voltage, the output voltage and the maximum load current. refer to table?7 for specific external capacitor requirements for a particular application. v in to v out step-down ratios there are restrictions in the maximum v in and v out step down ratio that can be achieved for a given input voltage due to the minimum off-time and minimum on-time limits of the regulator. the minimum off-time limit imposes a maximum duty cycle which can be calculated as: dc (max) = 1 C t off(min) ? f sw where t off(min) is the minimum off-time, 45ns typical for LTM4622A, and f sw is the switching frequency. conversely the minimum on-time limit imposes a minimum duty cycle of the converter which can be calculated as: dc (min) = t on(min) ? f sw where t on(min) is the minimum on-time, 20ns typical for LTM4622A. in the rare cases where the minimum duty cycle is surpassed, the output voltage will still remain in regulation, but the switching frequency will decrease from its programmed value. note that additional thermal derating may be applied. see the thermal considerations and output current derating section in this data sheet. lt m4622a rev b
10 for more information www.analog.com applications information output decoupling capacitors with an optimized high frequency, high bandwidth design, only single piece of 47f low esr output ceramic capaci - tor is required for each lt m4622 a output to achieve low output voltage ripple and very good transient response. additional output filtering may be required by the system designer, if further reduction of output ripples or dynamic transient spikes is required. table?7 shows a matrix of dif - ferent output voltages and output capacitors to minimize the voltage droop and overshoot during a 1a (50%) load step transient. multiphase operation will reduce effective output ripple as a function of the number of phases. application note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance will be more a function of stability and transient response. the linear technology ltpowercad ? design tool is avail - able to download online for output ripple, stability and transient response analysis and calculating the output ripple reduction as the number of phases implemented increases by n times. burst mode operation in applications where high efficiency at intermediate current are more important than output voltage ripple, burst mode operation could be used by connecting sync/mode pin to intv cc to improve light load efficiency. in burst mode operation, a current reversal comparator (i rev ) detects the negative inductor current and shuts off the bottom power mosfet, resulting in discontinuous operation and increased efficiency. both power mosfets will remain off and the output capacitor will supply the load current until the comp voltage rises above the zero current level to initiate another cycle. force continuous current mode (ccm) operation in applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. forced continuous operation can be enabled by tying the sync/mode pin to gnd. in this mode, induc - tor current is allowed to reverse during low output loads, the comp voltage is in control of the current comparator threshold throughout, and the top mosfet always turns output v oltage programming the pwm controller has an internal 0.6v reference voltage. as shown in the block diagram, a 60.4k 0.5% internal feedback resistor connects v out and fb pins together. adding a resistor r fb from fb pin to gnd programs the output voltage: r fb = 0.6v v out C 0.6v ? 60.4k table?1. v fb resistor table vs various output voltages (1% resistor) v out (v) 1.5 1.8 2.5 3.3 5.0 8.0 10.0 12.0 r fb (k) 40.2 30.1 19.1 13.3 8.25 4.87 3.83 3.16 pease note that for output above 3.3v, a higher operating frequency is required to optimize inductor current ripple. see operating frequency section. for parallel operation of n-channels LTM4622A, the fol - lowing equation can be used to solve for r fb : r fb = 0.6v v out C 0.6v ? 60.4k n input decoupling capacitors the ltm4622 a module should be connected to a low ac- impedance dc source. for each regulator channel, one piece 4.7f input ceramic capacitor is required for rms ripple current decoupling. bulk input capacitor is only needed when the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. the bulk capacitor can be an electrolytic aluminum capaci - tor and polymer capacitor. without considering the inductor current ripple, for each output, the rms current of the input capacitor can be estimated as : i cin(rms) = i out(max) % ? d ? 1C d ( ) where is the estimated efficiency of the power module. lt m4622a rev b
11 for more information www.analog.com applications information on with each oscillator pulse. during start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4622As output voltage is in regulation. operating frequency the operating frequency of the LTM4622A is optimized to achieve the compact package size and the minimum output ripple voltage while still keeping high efficiency. the default operating frequency is internally set to 1mhz. if any operating frequency other than 1mhz is required by application, the operating frequency can be increased by adding a resistor, r fset , between the freq pin and gnd, as shown in figure?29. the operating frequency can be calculated as: f hz ( ) = 3.2e11 324k||r fset ( ) please note a minimum switching frequency is required for given v in , v out operating conditions to keep a maximum peak-to-peak inductor ripple current below 1.2a for the LTM4622A. the peak-to-peak inductor ripple current can be calculated as : i p-p = v out 2.2 1 ? v out v in ? ? ? ? ? ? ? ? ? ? ? 1 f sw (mhz) the maximum 1.2a peak-to-peak inductor ripple current is enforced due to the nature of the valley current mode control to maintain output voltage regulation at no load. to reduce switching current ripple, 1.5mhz to 2mhz op - erating frequency is suggested for 5v and above output with r fset to gnd. v out 1.5v to 3.3v 5v, 8v 12v f sw 1mhz 1.5mhz 1.5mhz to 2mhz the operating frequency can also be decreased by adding a resistor between the freq pin and intv cc , calculated as: f hz ( ) = 1mhz ? 5.67e11 r fset ( ) the programmable operating frequency range is from 800khz to 4mhz. frequency synchronization the power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector. this allows the internal top mosfet turn-on to be locked to the rising edge of the external clock. the external clock frequency range must be within 30% around the set operating frequency. a pulse detection circuit is used to detect a clock on the sync/mode pin to turn on the phase-locked loop. the pulse width of the clock has to be at least 100ns. the clock high level must be above 2v and clock low level below 0.3v . the presence of an external clock will place both regulator channels into forced continuous mode operation. during the start-up of the regulator, the phase-locked loop function is disabled. multiphase operation for output loads that demand more than 2a of current, two outputs in the LTM4622A or even multiple ltm4622 as can be paralleled to run out of phase to provide more output current without increasing input and output voltage ripples. a multiphase power supply significantly reduces the amount of ripple current in both the input and output ca - pacitors. the rms input ripple current is reduced by, and the effective ripple frequency is multiplied by , the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). the output ripple amplitude is also reduced by the number of phases used when all of the outputs are tied together to achieve a single high output current design. the two switching mode regulator channels inside the ltm4622 a are internally set to operate 180 out of phase. multiple ltm4622 as could easily operate 90 degrees, 60 degrees or 45 degrees shift which corresponds to 4-phase, 6-phase or 8- phase operation by letting sync/mode of the ltm4622 a synchronize to an external multiphase oscillator like ltc ? 6902 . figure?2 shows a 4-phase design example for clock phasing. lt m4622a rev b
12 for more information www.analog.com the ltm4622 a device is an inherently current mode controlled device, so parallel modules will have very good current sharing. this will balance the thermals on the design. please tie run, track/ss, fb and comp pin of each paralleling channel together. figure?31 shows an example of parallel operation and pin connection. input rms ripple current cancellation application note 77 provides a detailed explanation of multiphase operation. the input rms ripple current can - cellation mathematical derivations are presented, and a graph is displayed representing the rms ripple current reduction as a function of the number of interleaved phases. figure?3 shows this graph. soft-start and output voltage tracking the track/ss pin provides a means to either soft-start the regulator or track it to a different power supply. a capacitor on the track/ss pin will program the ramp rate of the output voltage. an internal 1.4a current source will charge up the external soft-start capacitor towards intv cc voltage. when the track/ss voltage is below 0.6v , it will take over the internal 0.6v reference voltage to control the output voltage. the total soft-start time can be calculated as: t ss = 0.6 ? c ss 1.4a where c ss is the capacitance on the track/ss pin. current foldback and force continuous mode are disabled during the soft-start process. the ltm4622 a has internal 400s soft-start time when track/ss leave floating. applications information figure?3. input rms current ratios to dc load current as a function of duty cycle figure?2. example of clock phasing for 4-phase operation with ltc6902 4622a f02 v + 3.3v intv cc ph set ltc6902 200k 0 sync/mode v out1 8a 180 v out2 div gnd 90 sync/mode v out1 270 0 90 v out2 mod out1 out2 0.75 0.8 4622a f03 0.70.650.60.550.50.450.40.350.30.250.20.150.1 0.85 0.9 duty factor (v out /v in ) 0 dc load current rms input ripple current 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 1-phase 2-phase 3-phase 4-phase 6-phase lt m4622a rev b
13 for more information www.analog.com applications information output voltage tracking can also be programmed externally using the track/ss pin. the output can be tracked up and down with another regulator. figure?4 and figure?5 show an example waveform and schematic of a ratiometric tracking where the slave regulators output slew rate is proportional to the masters. the r fb(sl) is the feedback resistor and the r tr(top) / r tr(bot) is the resistor divider on the track/ss pin of the slave regulator, as shown in figure?5. following the upper equation, the masters output slew rate (mr) and the slave s output slew rate (sr) in volts/ time is determined by: mr sr = r fb(sl) r fb(sl) + 60.4k r tr(top) r tr(top) +r tr(bot) for example, v out(ma) = 1.5v , mr = 1.5v/ms and v out(sl) = 3.3v , sr = 3.3v/ms. from the equation, we could solve out that r tr(top) =?60.4k and r tr(bot) = 40.2k is a good combination for the ratiometric tracking. the track pins will have the 1.5a current source on when a resistive divider is used to implement tracking on that specific channel. this will impose an offset on the track pin input. smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. for example, where the 60.4k is used then a 6.04k can be used to reduce the track pin offset to a negligible value. the coincident output tracking can be recognized as a special ratiometric output tracking which the masters output slew rate (mr) is the same as the slaves output slew rate (sr), as waveform shown in figure?6. figure?5. example schematic of ratiometric output voltage tracking figure?6. output coincident tracking waveform time master output slave output output voltage 4622a f06 since the slave regulators track/ss is connected to the master s output through a r tr(top) /r tr(bot) resistor divider and its voltage used to regulate the slave output voltage when track/ss voltage is below 0.6v, the slave output voltage and the master output voltage should satisfy the following equation during the start-up. v out(sl) ? r fb(sl) r fb(sl) + 60.4k = v out(ma) ? r tr(top) r tr(top) +r tr(bot) figure?4. output ratiometric tracking waveform time slave output master output output voltage 4622a f04 40.2k 4622a f05 10f 25v v in 4v to 20v v out1 1.5v, 2a 47f 6.3v 0.1f v out1 v out2 3.3v, 2a 47f 6.3v v out2 fb1 comp1 comp2 freq gnd LTM4622A pgood1 pgood2 v in2 v in1 run1 run2 intv cc sync/mode track/ss1 track/ss2 13.3k 40.2k 60.4k fb2 v out1 lt m4622a rev b
14 for more information www.analog.com applications information from the equation, we could easily find out that, in the coincident tracking, the slave regulators track/ss pin resistor divider is always the same as its feedback divider. r fb(sl) r fb(sl) + 60.4k = r tr(bot) r tr(top) +r tr(bot) for example, r tr(top) = 60.4k and r tr(bot) = 13.3k is a good combination for coincident tracking for v out(max) = 1.5v and v out(sl) = 3.3v application. power good the pgood pins are open drain pins that can be used to monitor valid output voltage regulation. this pin monitors a 8% window around the regulation point. a resistor can be pulled up to a particular supply voltage for monitoring. to prevent unwanted pgood glitches during transients or dynamic v out changes, the LTM4622As pgood falling edge includes a blanking delay of approximately 40s. stability compensation the ltm4622 a module internal compensation loop is designed and optimized for low esr ceramic output capacitors only application. table?7 is provided for most application requirements. the ltpowercad design tool is available to down for control loop optimization. run enable pulling the run pin to ground forces the LTM4622A into its shutdown state, turning off both power mosfets and most of its internal control circuitry. trying the run pin voltage above 1.27v will turn on the entire chip. pre-biased output start-up there may be situations that require the power supply to start up with a pre-bias on the output capacitors. in this case, it is desirable to start up without discharging that output pre-bias. the LTM4622A can safely power up into a pre-biased output without discharging it. the ltm4622 a accomplishes this by forcing discontinuous mode (dcm) operation until the track/ss pin voltage reaches 0.6v reference voltage. this will prevent the bg from turning on during the pre-biased output start-up which would discharge the output. overtemperature protection the internal overtemperature protection monitors the junc - tion temperature of the module. if the junction temperature re aches approximately 160c , both power switches will be turned off until the temperature drops about 15c cooler. input overvoltage protection in order to protect the internal power mosfet devices against transient voltage spikes, the ltm4622 a constantly monitors each v in pin for an overvoltage condition. when v in rises above 22.5v, the regulator suspends operation by shutting off both power mosfets on the correspond - ing channel. once v in drops below 21.5v, the regulator immediately resumes normal operation. the regulator executes its soft-start function when exiting an overvolt - age condition. thermal considerations and output current derating the thermal resistances reported in the pin configura - tion section of the data sheet are consistent with those parameters defined by je sd51-9 and are intended for use with finite element analysis (fea) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation per - formed on a module package mounted to a hardware test board also defined by jesd51 -9 (test boards for area array surface mount package thermal measurements). the motivation for providing these thermal coefficients in found in jesd51-12 (guidelines for reporting and using electronic package thermal information). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the module regulator s thermal performance in their ap - plication at various electrical and environmental operating conditions to compliment any fea activities. without fea lt m4622a rev b
15 for more information www.analog.com applications information software, the thermal resistances reported in the pin con - figuration section are in-and-of themselves not relevant to providing guidance of thermal per formance; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to ones application usage, and can be adapted to correlate thermal performance to ones own application. the pin configuration section typically gives four thermal coefficients explicitly defined in jesd51-12; these coef - ficients are quoted or paraphrased below: 1. ja , the thermal resistance from junction to ambi - ent, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a je sd51-9 defined test board, which does not reflect an actual application or viable operating condition. 2. jcbottom , the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a jesd51-9 defined test board, which does not reflect an actual application or viable operating condition. 3. jctop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. 4. jb , the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the module and into the board, and is really the sum of the jcbottom and the thermal re - sistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package, using a two sided, two layer board. this board is described in jesd51-9. a graphical representation of the aforementioned ther - mal resistances is given in figure?7 ; blue resistances are contained within the module regulator , whereas green resistances are external to the module. figure?7. graphical representation of jesd51-12 thermal coefficients 4622a f07 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient thermal resistance components case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance lt m4622a rev b
16 for more information www.analog.com applications information as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by jesd51-12 or provided in the pin configuration section replicates or conveys normal op - erating conditions of a module. for example, in normal board-mounted applications, never does 100% of the device s total power loss (heat) thermally conduct exclu - sively through the top or exclusively through bottom of the module as the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the package granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. within a sip (system-in-package) module, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. to reconcile this complication without sacrificing modeling simplicitybut also, not ignoring practical realitiesan approach has been taken using fea software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) initially, fea software is used to accurately build the mechanical geometry of the module and the specified pcb with all of the correct material coefficients along with accurate power loss source definitions ; (2) this model simulates a software- defined jedec environment consistent with jesd51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the jedec-defined thermal resistance values; (3) the model and fea software is used to evaluate the module with heat sink and airflow ; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. an outcome of this process and due-diligence yields a set of derating curves provided in other sections of this data sheet. after these laboratory test have been performed and correlated to the module model, then the jb and ba are summed together to correlate quite well with the module model with no airflow or heat sinking in a properly define chamber. this jb + ba value is shown in the pin configuration section and should accurately equal the ja value because ap - proximately 100% of power loss flows from the junction through the board into ambient with no air flow or top mounted heat sink. the 1.5v, 3.3v, 5v, 8v and 12v power loss curves in figure?8 to figure?12 can be used in coordination with the load current derating curves in figure?13 to figure?23 for calculating an approximate ja thermal resistance for the ltm4622 a (in two-phase single output operation) with no heat sinking and various airflow conditions. the power loss curves are taken at room temperature, and are increased with multiplicative factors of 1.35 assuming junction temperature at 120c . the derating curves are plotted with the output current starting at 4a and the ambient temperature at 30c. these output voltages are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal mod - eling analysis. the junction temperatures are monitored while ambient temperature is increased with and without air flow. the power loss increase with ambient temperature change is factored into the derating curves. the junctions are maintained at 120c maximum while lowering output current or power with increasing ambient temperature. the decreased output current will decrease the internal module loss as ambient temperature is increased. the monitored junction temperature of 120c minus the ambient operat - ing temperature specifies how much module temperature rise can be allowed. as an example in figure? 16, the load current is derated to ~3a at ~100c with 200lfm air but not heat sink and the power loss for the 5v to 3.3v at 3a output is about 1.15w. the 1.15w loss is calculated with the ~0.85w room temperature loss from the 5v to 3.3v power loss curve at 3a , and the 1.35 multiplying factor. if the 100c ambient temperature is subtracted from the 120c junction temperature, then the difference of 20c divided by 1.15w equals a 17.5c/w ja thermal resis- tance. table?3 specifies a 17c/w C 18c /w value which is very close. tables 2 to 6 provide equivalent thermal resistances for 1.5v, 3.3v, 5v, 8v and 12v outputs with lt m4622a rev b
17 for more information www.analog.com figure?8. 1.5v output power loss figure?9. 3.3v output power loss figure?10. 5v output power loss applications information figure?11. 8v output power loss figure?12. 12v output power loss figure?13. 5v input to 1.5v output derating curve, no heat sink figure?14. 12v input to to 1.5v output derating curve, no heat sink figure?15. 16v input to 1.5v output derating curve, no heat sink figure?16. 5v input to 3.3v output derating curve, no heat sink lt m4622a rev b 3.5 power loss (w) 4622a f12 v in = 16v ambient temperature (c) 30 40 50 60 70 80 4 90 100 110 120 0 0.5 1.0 1.5 2.0 2.5 0 3.0 3.5 4.0 4.5 load current (a) 4622a f13 0lfm 200lfm 400lfm ambient temperature (c) 0.5 30 40 50 60 70 80 90 100 110 120 1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1.5 load current (a) 4622a f14 0lfm 200lfm 400lfm ambient temperature (c) 30 40 50 60 2.0 70 80 90 100 110 120 0 0.5 1.0 1.5 2.5 2.0 2.5 3.0 3.5 4.0 4.5 load current (a) 4622a f15 0lfm 200lfm power loss (w) 400lfm ambient temperature (c) 30 40 50 60 70 80 90 100 4622a f08 110 120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 load current (a) v in = 16v 4.0 4.5 load current (a) 4622a f16 0lfm 200lfm 400lfm v in = 12v v in = 5v load current (a) 0 0.5 1 1.5 2 2.5 0 3 3.5 4 0 0.5 1.0 1.5 2.0 2.5 power loss (w) 0.5 4622a f09 v in = 16v v in = 12v v in = 5v load current (a) 0 0.5 1 1.5 2 1 2.5 3 3.5 4 0 0.5 1.0 1.5 2.0 2.5 1.5 power loss (w) 4622a f10 v in = 16v v in = 12v load current (a) 0 0.5 1 1.5 2 2 2.5 3 3.5 4 0 0.5 1.0 1.5 2.0 2.5 2.5 power loss (w) 4622a f11 v in = 16v v in = 12v load current (a) 0 0.5 1 1.5 2 3 2.5 3 3.5 4 0 0.5 1.0 1.5 2.0 2.5
18 for more information www.analog.com applications information figure?18. 16v input to 3.3v output derating curve, no heat sink figure?19. 12v input to 5v output derating curve, no heat sink figure?17. 12v input to 3.3v output derating curve, no heat sink figure?20. 16v input to 5v output derating curve, no heat sink figure?21. 12v input to 8v output derating curve, no heat sink figure?22. 16v input to 8v derating curve, no heat sink figure?23. 16v input to 12v output derating curve, no heat sink lt m4622a rev b 100 4.5 load current (a) 4622a f20 0lfm 200lfm 400lfm ambient temperature (c) 30 40 50 110 60 70 80 90 100 110 120 0 0.5 1.0 120 1.5 2.0 2.5 3.0 3.5 4.0 4.5 load current (a) 4622a f21 0lfm 0 200lfm 400lfm ambient temperature (c) 30 40 50 60 70 80 90 0.5 100 110 120 0 0.5 1.0 1.5 2.0 2.5 3.0 1.0 3.5 4.0 4.5 load current (a) 4622a f22 0lfm 200lfm 400lfm ambient temperature (c) 30 1.5 40 50 60 70 80 90 100 110 120 0 2.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 load current (a) 2.5 4622a f23 0lfm 200lfm 400lfm 3.0 ambient temperature (c) 3.5 4.0 4.5 load current (a) 4622a f17 0lfm 200lfm 400lfm ambient temperature (c) 30 30 40 50 60 70 80 90 100 110 120 0 40 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 load current (a) 50 4622a f18 0lfm 200lfm 400lfm ambient temperature (c) 30 40 50 60 70 60 80 90 100 110 120 0 0.5 1.0 1.5 2.0 70 2.5 3.0 3.5 4.0 4.5 load current (a) 4622a f19 0lfm 200lfm 400lfm 80 ambient temperature (c) 30 40 50 60 70 80 90 100 110 90 120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
19 for more information www.analog.com table?2. 1.5v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja(c/w) figures 13, 14, 15 5, 12, 16 figure?8 0 none 19C20 figures 13, 14, 15 5, 12, 16 figure?8 200 none 17C18 figures 13, 14, 15 5, 12, 16 figure?8 400 none 17C18 table?3. 3.3v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja(c/w) figures 16, 17, 18 5, 12, 16 figure?9 0 none 19C20 figures 16, 17, 18 5, 12, 16 figure?9 200 none 17C18 figures 16, 17, 18 5, 12, 16 figure?9 400 none 17C18 table?4. 5v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja(c/w) figures 19, 20 12, 16 figure?10 0 none 19C20 figures 19, 20 12, 16 figure?10 200 none 17C18 figures 19, 20 12, 16 figure?10 400 none 17C18 table?5. 8v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja(c/w) figures?21, 22 5, 12 figure?11 0 none 19C20 figures?21, 22 5, 12 figure?11 200 none 17C18 figures?21, 22 5, 12 figure?11 400 none 17C18 table?6. 12v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja(c/w) figure?23 5, 12 figure?12 0 none 19C20 figure?23 5, 12 figure?12 200 none 17C18 figure?23 5, 12 figure?12 400 none 17C18 applications information lt m4622a rev b
20 for more information www.analog.com applications information table?7. output voltage response for each regulator channel vs component matrix (refer to figure?24) 1.0a load step typical measured values c in (ceramic) part number value c out1 (ceramic) part number value c out2 (bulk) part number value murata grm188r61e475ke11# 4.7f, 25v, 0603, x5r murata grm21r60j476me15# 47f, 6.3v, 0805, x5r panasonic 6tpc150m 150f, 6.3v 3.5 2.8 1.4mm murata grm188r61e106ma73 # 10f, 25v, 0603, x5r murata grm188r60j226m ea0 # 22f, 6.3v, 0603, x5r taiyo yuden tmk212bj475kg-t 4.7f, 25v, 0805, x5r taiyo yuden jmk212bj476mg-t 47f, 6.3v, 0805, x5r v out (v) c in (ceramic) (f) c in (bulk) c out1 (ceramic) (f) c out2 (bulk) (f) c ff (pf) v in (v) droop (mv) p-p derivation (mv) recovery time (s) load step (a) load step slew rate (a/s) r fb (k) 1.5 10 0 1 47 0 10 5, 12 0 89 10 1.0 10 40.2 1.5 10 0 1 4.7 150 0 5, 12 0 75 20 1.0 10 40.2 2.5 10 0 1 47 0 10 5, 12 0 112 10 1.0 10 19.1 2.5 10 0 1 4.7 150 0 5, 12 0 92 25 1.0 10 19.1 3.3 10 0 1 47 0 10 5, 12 0 144 15 1.0 10 13.3 3.3 10 0 1 4.7 150 0 5, 12 0 104 30 1.0 10 13.3 5 10 0 2 47 0 10 12 0 157 25 1.0 10 8.25 5 10 0 1 4.7 150 0 12 0 137 50 1.0 10 8.25 8 10 0 2 47 0 10 12 0 234 50 1.0 10 4.87 8 10 0 2 4.7 150 0 12 0 149 70 1.0 10 4.87 12 10 0 3 47 0 10 16 0 301 50 1.0 10 3.16 12 10 0 3 4.7 150 0 16 0 177 80 1.0 10 3.16 lt m4622a rev b
21 for more information www.analog.com applications information figure? 24 and figure? 25 show measured temperature picture of the LTM4622A with no heat sink from 12v input down to 3.3v and 5v output with 2a dc current on each and from 12v down to 5v and 8v output with 2a dc current on each. both without heat sink and airflow. safety considerations the ltm4622 a modules do not provide galvanic isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. the device does support thermal shutdown and over current protection. and without airflow. the derived thermal resistances in tables 2 to 6 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. room temperature power loss can be derived from the efficiency curves in the typical performance characteristics section and ad - justed with the above ambient temperature multiplicative factors. the printed cir cuit board is a 1.6mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. the pcb dimensions are 95mm 76mm. lt m4622a rev b
22 for more information www.analog.com applications information figure?24. thermal image, 12v input, 3.3v and 5v output, 2a?each, no airflow and no heat sink figure?25. thermal image, 12v input, 5v and 8v output, 2a?each, no airflow and no heat sink lt m4622a rev b
23 for more information www.analog.com applications information figure?26. recommended pcb layout layout checklist/example the high integration of ltm4622 a makes the pcb board layout very simple and easy. however, to optimize its electrical and thermal performance, some layout con - siderations are still necessary. ? use large pcb copper areas for high current paths, including v in1 , v in2 , gnd, v out1 and v out2 . it helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci - tors next to the v in , pgnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the?unit. ? the two dedicated input decoupling capacitors, one for each v in , closely placed on each side of the module. ? t o minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ? do not put via directly on the pad, unless they are capped or plated over. ? use a separated sgnd ground copper area for com - ponents connected to signal pins. connect the sgnd to gnd underneath the unit. ? for parallel modules, tie the v out , v fb , and comp pins together. use an internal layer to closely connect these pins together. the track pin can be tied a common capacitor for regulator soft-start. ? bring out test points on the signal pins for monitoring. figure? 26 gives a good example of the recommended layout. 4622a f26 gnd v out2 v out1 v in2 v in1 lt m4622a rev b
24 for more information www.analog.com figure?27. 8v in to 20v in , 3.3v and 5v output at 2a design applications information 13.3k 4622a f27 v in 8v to 20v v out1 3.3v, 2a 47f 0.1f 0.1f v out1 v out2 5v, 2a 47f v out2 fb1 comp1 comp2 freq gnd LTM4622A pgood1 pgood2 v in2 v in1 run2 run1 intv cc sync/mode track/ss1 track/ss2 8.25k fb2 10f 10f 6.65k 4622a f28 v out 3.3v, 4a 47f 2f 0.1f v out1 v out2 fb1 comp1 comp2 freq gnd LTM4622A pgood1 pgood2 intv cc pgood sync/mode track/ss1 track/ss2 fb2 v in 4v to 20v v in2 v in1 run2 run1 10f 10f 3.16k 4622a f29 v out1 12v, 2a 47f 0.1f 0.1f v out1 v out2 8v, 2a 47f v out2 fb1 comp1 comp2 freq gnd LTM4622A pgood1 pgood2 intv cc sync/mode track/ss1 track/ss2 4.87k fb2 324k v in 16v to 20v v in2 v in1 run2 run1 10f 10f figure?28. 4v in to 20v in , 3.3v two phase in parallel 4a design figure?29. 16v in to 20v in , 12v and 8v output at 2a with 2mhz switching frequency lt m4622a rev b
25 for more information www.analog.com applications information figure?30. 4v in to 20v in , 1.5v and 3.3v output at 2a design with output coincident tracking 0.1f 13.3k 60.4k v out1 40.2k 4622a f30 v out1 1.5v, 2a 47f v out1 v out2 3.3v, 2a 47f v out2 fb1 comp1 comp2 freq gnd LTM4622A pgood1 pgood2 intv cc sync/mode track/ss1 track/ss2 13.3k fb2 v in 4v to 20v v in2 v in1 run2 run1 10f 10f 10k 10f 4 v in 4v to 20v v out 1.5v, 8a 1f 47f 4 0.1f v out1 v out2 fb1 comp1 comp2 freq gnd LTM4622A pgood1 pgood2 pgood v in2 run1 v in1 run2 intv cc intv cc sync/mode track/ss1 track/ss2 fb2 4622a f31 v out1 v out2 fb1 comp1 comp comp fb comp2 freq gnd LTM4622A pgood1 pgood2 v in2 run1 v in1 run2 intv cc pgood sync/mode track/ss1 track/ss2 fb2 set mod out3 gnd out4 ltc6902 200k v + div out2 ph out1 fb figure?31. 4 phase, 1.5v output at 8a design with ltc6902 lt m4622a rev b
26 for more information www.analog.com package description LTM4622A component lga and bga pinout pin id function pin id function pin id function pin id function pin id function a1 v out2 a2 v in2 a3 track/ss2 a4 fb2 a5 comp2 b1 v out2 b2 run2 b3 v in2 b4 pgood2 b5 gnd c1 gnd c2 gnd c3 intv cc c4 freq c5 sync/mode d1 v out1 d2 run1 d3 v in1 d4 pgood1 d5 gnd e1 v out1 e2 v in1 e3 track/ss1 e4 fb1 e5 comp1 package row and column labeling may vary among module products. review each package layout carefully. lt m4622a rev b
27 for more information www.analog.com package description please refer to http://www.linear.com/product/LTM4622A#packaging for the most recent package drawings. package top view 4 pin ?a1? corner y x aaa z aaa z detail a package bottom view 3 see notes suggested pcb layout top view 0.000 2.540 1.270 1.270 2.540 2.540 1.270 2.540 1.270 0.3175 0.3175 0.000 e d c b a 12345 pin 1 ?b (25 places) d e e b f g detail a 0.3175 0.3175 lga 25 0613 rev ? ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? lga package 25-lead (6.25mm 6.25mm 1.82mm) (reference ltc dwg # 05-08-1949 rev ?) 7 see notes notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222, spp-010 5. primary datum -z- is seating plane 6. the total number of pads: 25 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature 7 package row and column labeling may vary among module products. review each package layout carefully ! detail b detail b substrate mold cap // bbb z z a symbol a b d e e f g h1 h2 aaa bbb eee min 1.72 0.60 0.27 1.45 nom 1.82 0.63 6.25 6.25 1.27 5.08 5.08 0.32 1.50 max 1.92 0.66 0.37 1.55 0.15 0.10 0.15 notes dimensions total number of lga pads: 25 h2 h1 s yx z? eee lt m4622a rev b
28 for more information www.analog.com package description please refer to http://www.linear.com/product/LTM4622A#packaging for the most recent package drawings. package top view 4 pin ?a1? corner y x aaa z aaa z detail a package bottom view 3 see notes suggested pcb layout top view 0.000 2.540 1.270 1.270 2.540 0.630 0.025 2.540 1.270 2.540 1.270 0.3175 0.3175 0.000 e d c b a 12345 pin 1 notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature ?b (25 places) a detail b package side view m x yzddd m zeee a2 d e e b f g detail a 0.3175 0.3175 bga 25 0517 rev a ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? bga package 25-lead (6.25mm 6.25mm 2.42mm) (reference ltc dwg # 05-08-1502 rev a) 6 see notes symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 2.22 0.50 1.72 0.60 0.60 0.27 1.45 nom 2.42 0.60 1.82 0.75 0.63 6.25 6.25 1.27 5.08 5.08 0.32 1.50 max 2.62 0.70 1.92 0.90 0.66 0.37 1.55 0.15 0.10 0.20 0.30 0.15 total number of balls: 25 dimensions notes ball ht ball dimension pad dimension substrate thk mold cap ht z 5. primary datum -z- is seating plane 6 package row and column labeling may vary among module products. review each package layout carefully ! detail b substrate a1 ccc z z // bbb z h2 h1 b1 mold cap lt m4622a rev b
29 for more information www.analog.com information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. revision history rev date description page number a 11/17 corrected pin configuration. swapped v in1 and v in2 . 2 b 4/18 corrected r fset to gnd 9, 11 lt m4622a rev b
30 for more information www.analog.com ? analog devices, inc. 2017-2018 d16848-0-4/18(b) www.analog.com related parts package photos part number description comments ltm4614 dual 5v, 4a module regulator 2.375v v in 5.5v, 0.8v v out 5v, 15mm 15mm 2.82mm lga ltm4618 26v in , 6a step-down module regulator 4.5v v in 26.5v, 0.8v v out 5v, pll input, v out tracking, 9mm 15mm 4.32mm lga lt m4619 dual 26v, 4a step-down module regulator 4.5v v in 26.5v, 0.8v v out 5v, pll input, v out tracking, pgood, 15mm 15mm 2.82mm lga lt m4622 lower v out than LTM4622A 3.6v v in 20v. 0.6v v out 5.5v, pin compatible with LTM4622A ltm4623 20v in , 3a step-down module regulator 4v v in 20v, 0.6v v out 5.5v, pll input, clkout, v out tracking, pgood, 6.25mm 6.25mm 1.82mm lga lt m4624 14v in , 4a step-down module regulator 4v v in 14v, 0.6v v out 5.5v, v out tracking, pgood, 6.25mm 6.25mm 5.01mm bga lt m4625 20v in , 5a step-down module regulator 4v v in 20v, 0.6v v out 5.5v, pll input, clkout, v out tracking, pgood, 6.25mm 6.25mm 5.01mm bga lt m4631 ultrathin, dual 10a step-down module regulator 4.5v v in 15v, 0.6v v out 1.8v, 16mm 16mm 1.91mm lga ltm4642 20v in , dual 4a, step-down module regulator 4.5v v in 20v, 0.6v v out 5.5v, 9mm 11.25mm 4.92mm bga ltm4643 ultrathin, quad 3a, step-down module regulator 4v v in 20v, 0.6v v out 3.3v, 9mm 15mm 1.82mm lga ltm4644 quad 4a, step-down module regulator 4v v in 14v, 0.6v to 5.5v, 9mm 15mm 5.01mm bga lt c6902 multiphase oscillator with spread spectrum frequency modulation 1-, 3-, or 4-phase outputs; to 20mhz frequency design resources subject description module design and manufacturing resources design: ? selector guides ? demo boards and gerber files ? free simulation t ools manufacturing: ? quick start guide ? pcb design, assembly and manufacturing guidelines ? package and board level reliability module regulator products sear ch 1. sort table of products by parameters and download the result as a spread sheet. 2. sear ch using the quick power search parametric table. techclip videos quick videos detailing how to bench test electrical and thermal performance of module products. digital power system management linear technologys family of digital power supply management ics are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature eeprom for storing user configurations and fault logging. lt m4622a rev b

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